1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to apparatuses and methods for manufacturing dense metal programmable read only memory.
2. Description of the Related Art
Semiconductor memory devices are widely used in the manufacture of digital equipment, such as microprocessor systems. To store fixed, commonly used programs, microprocessor systems generally use Read Only Memory devices or xe2x80x9cROMsxe2x80x9d, such as the basic input/output system (BIOS) ROM for computer systems.
Semiconductor ROMs are typically configured as an array memory cells, wherein each individual memory cell is coupled to both a wordline and a bitline. To select a particular memory cell during a read operation, memory accessing circuitry is commonly utilized. For example, memory access circuit components typically include addressing circuitry for selecting a memory cell, wordline drivers for driving a selected wordline, sense amplifiers for amplifying the signals read from the selected memory cell, and output buffers for driving data out of the memory.
FIG. 1 is a schematic diagram of a conventional diffusion programmable ROM cell array 10. The diffusion programmable ROM cell array 10 includes a plurality of wordlines 12, a plurality of bitlines 14, and a plurality of memory cells 16, each at the intersection of a wordline 12 and a bitline 14. It should be noted that the wordlines 12 and bitlines 14 occupy different levels of the semiconductor, and thus do not physically intersect.
In use, the wordlines 12 function as addresses for memory cells 16, while the bitlines 14 function as the output of the cell array 10. When manufacturing the diffusion programmable ROM cell array 10, each memory cell 16 is programmed to output either a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d when the wordline 12 addressing it is activated. Generally, a wordline 12 in a diffusion ROM is activated when it is asserted high. As described in greater detail subsequently, each memory cell 16 is programmed as a xe2x80x9c1xe2x80x9d cell or a xe2x80x9c0xe2x80x9d cell during manufacturing, depending on the desired functionality of the ROM.
During a memory read operation, the ROM receives a memory address of a desired memory location within the memory cell array 10 from an address bus. The memory address, or a portion thereof, is then forwarded to an address decoder, which decodes the address and asserts one of the wordlines 12 in the memory cell array 10 high, thus activating it, all other wordlines 12 remain low. Thereafter, depending on the programming of the ROM, each bitline 14 will output either a logical xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d In effect, by programming the various memory cell locations of the ROM, each wordline 12 can be used to select a particular binary output combination from the bitlines 14.
FIG. 2 is a schematic diagram showing a magnified view of a conventional diffusion programmable ROM cell array 18. The conventional diffusion programmable ROM cell array 18 includes wordlines 12a and 12b, bitlines 14a and 14b, and memory cell transistors 16a-16d. 
As shown in FIG. 2, each memory cell of the diffusion programmable ROM memory cell array is actually a transistor 16a-16d. Further, the gate of each memory cell transistor 16a-16d is coupled to a wordline 12a/12b, and a first terminal of each memory cell transistor 16a-16d is coupled to a bitline 14a/14b. Finally, a second terminal of each memory cell transistor 16a-16d is coupled to ground.
Initially, a precharge circuit is used to charge each bitline 14a/14b high, such that a logic xe2x80x9c1xe2x80x9d is read out from each memory cell. Thereafter, depending on the programming of the memory cell array, each bitline 14a/14b will either remain high or be drawn low when a particular wordline 12a/12b is activated.
For example, memory cell transistor 16a functions such that when wordline 12a is low, memory cell transistor 16a is shut off, and therefore bitline 14a maintains its state, generally high. However, when wordline 12a is asserted high, memory cell transistor 16a turns on, allowing the bitline 14a to be drawn to ground, thus pulling the bitline 14a low. Since memory cell transistor 16a allows the bitline 14a to be drawn low, it is called a xe2x80x9c0xe2x80x9d cell.
For a memory cell to allow the bitline to remain high when the wordline 12 is asserted, it must be programmed as a xe2x80x9c1xe2x80x9d cell. In a diffusion programmable ROM, the memory cell transistor 16a-16d is simply disabled to create a xe2x80x9c1xe2x80x9d cell. For example, memory cell transistor 16d has been disabled, illustrated by its non-connection to the bitline 14b. Thus, regardless of the state of the wordline 12b, the memory cell transistor 16d will not pull the bitline 14b low, and therefore the bitline 14b will maintain its state, which is generally high.
FIG. 3A is an illustration showing a conventional diffusion programmable ROM memory cell 16a, programmed as a xe2x80x9c0xe2x80x9d cell. The xe2x80x9c0xe2x80x9d cell 16a includes a wordline 12 coupled to a diffusion layer 20, a bitline contact 22 coupling the diffusion layer 20 to a bitline 14, and a ground diffusion wire 24 that is coupled to ground.
As stated previously, initially the bitline 14 is charged high to a logical xe2x80x9c1.xe2x80x9d While the wordline 12 is low, the bitline 14 remains high because the diffusion layer 20 isolates the bitline contact 22 from the ground diffusion wire 24. However, when the wordline 12 is asserted high, the bitline 14 is pulled low because the diffusion layer 20 becomes conductive when the wordline 12 is high. Specifically, asserting the wordline 12 high charges the diffusion layer 20 and causes it to conduct, creating a connection between the bitline contact 22 and the ground diffusion wire 24. Since the bitline 14 is coupled to the bitline contact 22, and thus to the ground diffusion wire 24 via the diffusion layer 20, the bitline 14 is pulled low.
FIG. 3B is an illustration showing a conventional diffusion programmable ROM memory cell 16d, programmed as a xe2x80x9c1xe2x80x9d cell. The xe2x80x9c1xe2x80x9d memory cell 16d includes a wordline 12, a diffusion layer 20 separated into a first portion 26a and a second portion 26b, a bitline contact 22 coupling the first portion 26a of the diffusion layer 20 to a bitline 14, and a ground diffusion wire 24 coupling the second portion 26b of the diffusion layer 20 to ground.
Similar to the xe2x80x9c0xe2x80x9d cell, the xe2x80x9c1xe2x80x9d memory cell 16d initially has the bitline 14 charged high to a logical xe2x80x9c1.xe2x80x9d While the wordline 12 is low, the bitline 14 remains high because the diffusion layer 20 isolates the bitline contact 22 from the ground diffusion wire 24. However, unlike the xe2x80x9c0xe2x80x9d cell, the xe2x80x9c1xe2x80x9d cell allows the bitline 14 to remain high when the wordline 12 is asserted high. Specifically, since the diffusion layer 20 is removed from around the wordline 12, the diffusion layer 20 is not charged when the wordline 12 is asserted high, and thus, a connection is not formed between the bitline contact 22 and the ground diffusion wire 24. Hence, the bitline 14 is never pulled low in the xe2x80x9c1xe2x80x9d memory cell 16b. 
FIG. 4 is an illustration showing a conventional diffusion programmable ROM cell array 30 configuration, comprising two memory cells. The conventional diffusion programmable ROM cell array 30 includes a first memory cell 32 and a second memory cell 34. The first memory cell 32 includes a first wordline 12a coupled to a diffusion layer 20, a shared bitline contact 22 coupling a bitline 14 to the diffusion layer 20, and a first ground diffusion wire 24a coupling the diffusion layer 20 to ground.
The second memory cell 34 shares the diffusion layer 20 with the first memory cell 32, and includes a second wordline 12b coupled to the diffusion layer 20. The second memory cell 34 also includes the shared bitline contact 22, which couples the bitline 14 to the diffusion layer 20, and a second ground diffusion wire 24b coupling the diffusion layer 20 to ground.
In operation, the first wordline 12a is utilized to address the first memory cell 32, and the second wordline 12b is utilized to address the second memory cell 34, both of which can affect the bitline 14.
For the first memory cell 32, the bitline 14 is initially charged high to a logical xe2x80x9c1.xe2x80x9d While the first wordline 12a is low, the bitline 14 maintains its state, usually high, because the diffusion layer 20 isolates the shared bitline contact 22 from the first ground diffusion wire 24a. However, when the first wordline 12a is asserted high, the bitline 14 is pulled low because the diffusion layer 20 becomes conductive between the shared bitline contact 22 and the first ground diffusion wire 24a. 
Specifically, asserting the first wordline 12a high charges the diffusion layer 20 between the shared bitline contact 22 and the first ground diffusion wire 24a and causes it to conduct, thus creating a connection between the shared bitline contact 22 and the first ground diffusion wire 24a. Since the bitline 14 is coupled to the shared bitline contact 22, and therefore also to the first ground diffusion wire 24a via the diffusion layer 20, the bitline 14 is pulled low.
The second memory cell 34 operates in a similar manner. Specifically, asserting the second wordline 12b high charges the diffusion layer 20 between the shared bitline contact 22 and the second ground diffusion wire 24b and causes it to conduct, thus creating a connection between the shared bitline contact 22 and the second ground diffusion wire 24b. Since the bitline 14 is coupled to the shared bitline contact 22, and therefore also to the second ground diffusion wire 24b via the charged diffusion layer 20, the bitline 14 is pulled low.
Today""s semiconductor processes are complicated requiring dozens of steps, each taking up time and introducing materials handling and inventor factors. Further, customers require the turn-around time or cycle time to be kept as short as possible. However, since the code for data and programs stored in the ROM are fixed at the time of manufacture, a mistake in the ROM code results in wasted ROM wafers. For example, if the ROM includes program code, and a bug is later discovered in the program code, wafers containing ROMs are wasted if the wafers have already proceeded past the processing step required for programming the ROMs.
For this reason, programming should be done as late in the manufacturing process as possible. However, since the diffusion layer must be formed early in the manufacturing process, a diffusion programmable ROM must be programmed early in the manufacturing process. In response to this shortcoming, metal or via programmable ROMs were developed that allow late process programming.
FIG. 5 is an illustration showing a conventional via programmable ROM cell array 40 configuration, comprising two memory cells. The via programmable ROM cell array 40 includes a first memory cell 42 and a second memory cell 44. The first memory cell 42 includes a first diffusion layer 20a coupled to a first wordline 12a, a first ground diffusion wire 24a, a first metal to diffusion contact 22a which couples a first m1 pad 46a to the drain diffusion 20a of the first memory cell 42, and a first m2 to m1 via 22b which couples the first m1 pad 46a to the m2 bitline 14. Similarly, the second memory cell 44 includes a second diffusion layer 20b coupled to a second wordline 12b, a second ground diffusion wire 24b,a second diffusion contact 22c, a second m1 pad 46b, and a second m2 to m1 via 22d which couples to the bitline 14.
The via-programmable ROM cell array 40 operates similar to the diffusion programmable ROM cell array discussed previously. Specifically, in the first memory cell 42, when the first wordline 12a is low, the first diffusion layer 20a is nonconductive, and therefore current cannot be conducted through the first m2 to m1 via 22b to the first m1 pad 46a down through the first metal to diffusion contact 22a to the ground diffusion wire 24a. When the first wordline 12a is asserted high, the first diffusion layer 20a becomes charged and therefore conductive, thus forming a conduction path between the first metal to diffusion contact 22a and the first m1 pad 46a and the first m2 to m1 via 22b and the diffusion ground wire 24a. Since the bitline 14 is coupled to first m2 to m1 via 22b via the first m1 pad 46a and the first metal to diffusion contact 22a, the bitline 14 goes low, resulting in a logical xe2x80x9c0.xe2x80x9d The second memory cell 44 operates in a similar manner.
Both the first and second memory cells 42 and 44 are xe2x80x9c0xe2x80x9d cells because they allow the bitline 14 to go low when their corresponding wordline 12a/12b is selected. To make a via programmable ROM memory cell a xe2x80x9c1xe2x80x9d cell, the bitline m2 to m1 via is removed. For example, removing the first bitline m2 to m1 via 22b will program the first memory cell 42 to a xe2x80x9c1xe2x80x9d cell.
Since the memory cells in a metal programmable ROM are programmed by altering a via layer rather than the diffusion layer, a via programmable ROM can be programmed later in the manufacturing process, when the via layers are formed. In this manner, production can be initiated on a wafer of via programmable ROMs, and held at a later stage in the manufacturing process. Micro-code for the ROMs can be upgraded with a minimal amount of time used to finish the wafers. Thus, via programmable ROMs provide greater flexibility than diffusion programmable ROMs.
However, as shown in FIG. 5, the bitline contacts 22a/22c, m1 pads 46a/46b, and m2 to m1 vias 22b/22d cannot be shared in the via programmable ROM memory cell array 40. Hence, each memory cell 42/44 must be formed on a separate portion of diffusion, resulting in wasted space 50. More particularly, the space 50 between the first m1 pad 46a and the second m1 pad 46b is wasted. Thus, conventional via programmable ROMs are less dense, and consequently larger, than conventional diffusion programmable ROMs.
As a result, semiconductor chip designers conventionally had to choose between the flexibility provided by metal programmable ROMs, and the density provided by diffusion programmable ROMs.
Further, there exist minimum size rules that restrict the minimum size of a piece of diffusion used in semiconductor manufacturing to a predetermined minimum diffusion size, as a result of manufacturing limitations of other semiconductor manufacturing processes. Thus, a transistor designed on a very small portion of diffusion will be restricted to using a larger diffusion size if the particular designed size of diffusion is smaller than the predetermined minimum diffusion size.
Thus, each xe2x80x9c1xe2x80x9d cell of a conventional diffusion programmable ROM requires two separate portions of diffusion, each being no smaller than the predetermined minimum diffusion size. Similarly, all memory cells of a conventional via programmable ROM are formed on separate portions of diffusion, each being no smaller than the predetermined minimum diffusion size. Thus, there is a minimum size to which conventional programmable ROMs may be designed.
In view of the forgoing, there is a need for improved methods for manufacturing a programmable ROM. The method provide the manufacturing flexibility of a via/metal programmable ROM, while providing the density of a diffusion programmable ROM.
Broadly speaking, the present invention fills these needs by providing a dense metal programmable ROM using a NAND/NOR architecture. In one embodiment, a metal programmable ROM is disclosed. The metal programmable ROM includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.
In another embodiment, the metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines, as in the first embodiment, and a group of transistors coupled to a subset of the wordlines. The group of transistors includes a first transistor having a first terminal coupled to a bitline, and a gate terminal coupled to one of the wordlines in the subset of wordlines. The group of transistors also includes a second transistor having a second terminal coupled to ground, and a second gate terminal coupled to another wordline of the subset of wordlines.
A method for manufacturing a metal programmable ROM is disclosed in yet a further embodiment. Initially, a group of memory cells are formed, with each memory cell connected to a corresponding wordline of the metal programmable ROM. Each of the memory cells in the memory cell group is then interconnected between a single bitline connection and the ground. Further, the memory cells are programmed by shorting a transistor associated with the programmed memory cell.
Configuring memory cell groups of the memory array in a NAND type arrangement allows the memory cells of the memory cell group to share one bitline contact. Advantageously, the contact sharing configuration of the present invention reduces the bitline load and allows for a denser cell array.
Further, groups of memory cells of the present invention are formed on a single portion of diffusion, and more than one memory cell group may occupy the single portion of diffusion. Thus, there are generally no concerns about minimum diffusion size. As a result, both xe2x80x9c1xe2x80x9d cell and xe2x80x9c0xe2x80x9d cell memory transistors may be made smaller than is possible with conventional via/metal programmable ROMs. Consequently, the dense metal programmable ROM of the present invention can be made smaller and denser than conventional via/metal programmable ROMs.
Moreover, the metal programmable ROM of the present invention is programmed at the metal layer, rather than the diffusion level. As a result, the present invention provides increased flexibility because the metal programmable ROM wafers may be held at the metal level, thus allowing for quicker production parts after a design code change.